The Cadence Simulation VIP is ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Cadence Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- The most widely used AHB VIP
- Includes support for APB
- Part of a complete AMBA verification solution including Interconnect Verification
- Features optional Assertion-Based VIP and Accelerated VIP