The AMBA AXI3 Verification IP provides an effective & efficient way to verify the components interfacing with AMBA® AXI3 bus of an ASIC/FPGA or SoC.
The AMBA AXI3 VIP is fully compliant with standard AMBA® AXI3 specification from ARM. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.
- Compliant to AMBA® AXI3 specifications from ARM.
- Support for all type of AMBA AXI3 devices.
- Parametrized data and address bus.
- Support for all protocol Burst Types, Burst Lengths and Response
- Supports out of order transactions with parametrized out of order
- Strong protocol checking Bus Monitor which also provides
- statistics of the transactions.
- Configurable modes for Valid and Ready on different channels.
- Supports data interleaving on both read and write channel.
- Supports unaligned data transfers.
- Supports Privilege and Secure accesses and Configurable Memory.
- Support exclusive and locked transfers.
- Supports endianness check and conversion.
- Dynamic configuration is supported.
- Supports transaction logging with detailed description of each
- Supporst UVM_RAL Model.
- Provides detailed performance monitoring for all the transfers.
- Supports advanced System Verilog features like constrained
- random testing.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions, static
- and dynamic assertion.
- Built in Extensive Coverage Across the Channels.
- Provides a comprehensive user API (callbacks) in all BFMs.
- Graphical analyser to show transactions for easy debugging.
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration
- in IP and SoC environment
- AMBA AXI3 Master/Slave Agent
- AMBA AXI3 Bus Monitor and Score boarding
- AMBA AXI3 Interconnect Model (Optional)
- Test Environment & Test Suite :
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & cover point Tests
- Integration Guide, User Manual and Release Notes
Block Diagram of the AMBA AXI3 Verification IP Verification IP