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CAN Bus 2.0 Master and Slave UVM Verification IP
The CAN Bus VIP (Controller Area Network) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this CAN Bus 2.0 VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The CAN Bus VIP has been interoperability tested with both Slave and Master VIP configurations and comes with a Bus Monitor for performing all protocol checks. The monitor also performs key protocol checks and reports errors for non-compliance with CAN Bus Part A and B specifications.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
The CAN Bus VIP has been interoperability tested with both Slave and Master VIP configurations and comes with a Bus Monitor for performing all protocol checks. The monitor also performs key protocol checks and reports errors for non-compliance with CAN Bus Part A and B specifications.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
Features
- Overview
- VIP: CAN Bus Master and Slave
- Compliance: ISO 11898 CAN 2.0 Part A & B, CAN FD 1.0
- Language: System Verilog
- Methodology: UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- Technical Specifications
- CAN 2.0 (A/B) and CAN FD 1.0
- Bit rates up to 1 Mb/s
- Two reset mechanisms
- Software reset
- System reset
- Transmit message First In First Out (FIFO) with a user-configurable depth of up to 64 messages
- Transmit prioritization through one High-Priority Transmit buffer
- Automatic re-transmission on errors or arbitration loss
- Acceptance filtering (through a user-configurable number) of up to 4 acceptance filters
- Supports Normal and Configuration modes
- Supports Sleep Mode with automatic wakeup
- Supports Loop Back Mode for diagnostic applications
- Supports Maskable Error and Status Interrupts, Readable Error Counters, Bit Timing Logic and Bit Stream Processor
Deliverables
- CAN 2.0 Master or Slave VIP
- Sample Testbench integrated with proven XILINX CAN 2.0 IP
- Sample Scoreboard
- Sample Virtual Sequencer
- VIP User Guide
Block Diagram of the CAN Bus 2.0 Master and Slave UVM Verification IP
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