Double-Data-Rate-Two Synchronous Dynamic Random Access Memory (DDR2 SDRAM) is the memory technology used for high speed data transfer. This class of memory technology has 4n pre-fetch architecture and transfers data on both edges of clock (positive and negative). DDR2 SDRAM Memory controller manages all the Initialization, Read, Write and Refresh requirements of DDR2 memory module.
DDR2 SDRAM VIP can be used to verify JEDEC Standard (JESD79-2D) based DDR2 SDRAM Memory Model(s).
- All command operations (Refresh, Self Refresh, Power Down, No Operation, Mode Register Set, Precharge, Precharge All, Bank Active, Read, Write, Read with Auto Precharge, Write with Auto Precharge, Deselect)
- Data transfer with Burst Length of 4/8
- Sequential/Interleaved Burst type
- Normal Mode command operations
- Extended Mode Registers (EMR1, EMR2 & EMR3)
- Variable Additive Latency (0 – 5 clocks) as per EMR1 configuration
- Differential signaling for DQS (or LDQS and UDQS) and RDQS signals
- Multiple Bank operations as per memory size support
- Truncated Read/Write command operations as per the specification
- Data Masking in Write command operations
- Posted Column Address Strobe (CAS) Read/Write command operations
- Seamless Read/Write command operations for bandwidth conservation
- Auto configuration of Timing Parameters as per the VIP model configuration and specification
- User configurable clock frequency model (400, 533, 667, 800)
- User configurable data port interface (x4, x8, x16)
- User configurable memory size (256 Mb, 512 Mb, 1 Gb, 2 Gb, 4 Gb)
- User configurable speed bins (3-3-3, 4-4-4, 5-5-5, 6-6-6)
- Functional Coverage for Coverage Driven Verification
- DDR2 JEDEC standard (JESD79-2D) Interface compliant protocol checks (assertions)
- Active/Passive VIP configuration to activate/de-activate its driver operation
- Plug and Play with better User Interface
- Error Injection Mechanism
- eInfochips provides customers regular product updates and expert consultation. Our Verification experts are available round the clock to meet customer requirements related to integrating verification components into test environment and other support related issues.
- JEDEC standard (JESD79-2D) compliant DDR2 SDRAM Verification IP
- Documentation – Verification Environment Plan, Verification Plan, Test Plan, Assertion Plan and Coverage Plan.
- Sample Verification Environment illustrating DDR2 SDRAM VIP instance and it’s active operations
- Verification Environment supporting Responder (DDR2 DUT emulator) and Data Integrity checking scoreboard modules
- Comprehensive Coverage Driven Verification test suite, scripts and other utilities
Block Diagram of the DDR2 SDRAM VIP Verification IP