Test and Verification Solutions contributes ETHERNET UVM/eRM VIP as a part of asureVIP™ offering. This is a highly flexible and configurable verification IP, which can be easily integrated into verification environment. VIP can be used for both functional verification & for emulator.
The TVS ETHERNET UVM/eRM VIP encompasses several modes for different signal transmission rates like 10Mbps, 100Mbps and 1000Mbps. It is programmed in System Verilog and supports UVM/eRM Testbenches.
The VIP comes with a UVM/eRM Monitor for checking the conformance of the design with the technical specifications. The monitor performs the protocol checks and reports errors for noncompliance of features with IEEE 802.3.
- Compatible with both Full and Half duplex modes & Speed of 10 , 100 & 1000 Mbps.
- Supports various interfaces like GMII, MII, RGMII and SGMII for allowing maximum flexibility when communicating between PHY and DTE.
- C++ transactor is integrated to provide Flow control , RXFIFO , WRFIFO Ethernet packet generation.
- Supports flow control by allowing programmable inter-frame gap and collision detection Techniques.
- Programmable error injection and detection.
- Programmable IFG , pause frame , Receiver Extract type , Payload data , preamble size , fake collision.
- Supports the following packet types:
- Standard Ethernet Frame
- Ethernet magic frame
- Ethernet VLAN Frame
- Ethernet Jumbo Frame
- Ethernet pause frame
- Highly Flexible, Independent and Configurable ETHERNET VIP.
- VIP user Guide
- ETHERNET UVM/eRM VIP
- Sample Testbench Integrated with proven XILINX ETHERNET CORE.
- Sample Scoreboard
- Sample Virtual Sequencer
Block Diagram of the Ethernet 10/100/1000Mbps UVM/eRM Verification IP