The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- Supports broadest range of MAC interfaces
- Supports Energy-Efficient Ethernet, Priority-based Flow Control, and Ethernet Audio/ Video
- Provides automotive Ethernet support
- Features optional Accelerated VIP