Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the Ethernet 100GPL protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for Ethernet 100GPL helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet 100GPL runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
The VIP for Ethernet 100GPL enables verification of Ethernet interfaces in standalone, partial stack, and full stack mode for speeds from 10Mbps to 400Gbps:
◾XMII level, that is, between MAC and PHY
◾Between PHY sub-layers, that is, PCS, PMA, PMD
◾Between link partners, that is, TX Station and RX Station
The VIP for Ethernet 100GPL complies with IEEE 802.3ck Ethernet standards and draft specifications. It supports other widely popular Ethernet interfaces, which are proprietary and based on IEEE 802.3.