Ethernet-TSN Verification IP
Ethernet-TSN VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Features
- Supports Time Sensitive transmission of data over Ethernet networks
- Full support for IEEE 802.1BA
- Full support for IEEE 802.1Qav
- Full support for IEEE 802.1Qat
- Full support for IEEE 802.1AS
- Full support for IEEE 802.1Qbv
- Full support for IEEE 802.1Qbu
- Full support for IEEE 802.1Qca
- Full support for IEEE 802.1CB
- Full support for IEEE 802.1Qcc
- Full support for IEEE 802.1Qci
- Full support for IEEE 802.1Qch
- Full support for IEEE 802.1CM
- Full support for IEEE 802.1Qcr
- Full support for IEEE 802.1CS
- Full support for IEEE 802.3br
- Supports 1G
- Supports GMII
- Supports TBI (i.e Output of 8b/10b PCS)
- Supports SGMII as per specification 1.8
- Supports QSGMII as per specification 1.2
- Supports USGMII as per specification 3.0 (5G and 10G)
- Supports RGMII/RTBI as per specification 2.0
- Supports 1000Base-KX
- Supports clause 73 backplane auto-negotiation for 1000Base-KX
- Supports clause 37 auto-negotiation
- Supports SGMII auto-negotiation
- Supports QSGMII auto-negotiation
- Supports USGMII auto-negotiation and packets
- Supports full duplex and half duplex of operation
- Supports 100M
- Supports MII
- Supports SMII as per specification 2.1
- Supports RMII as per specification 1.2
- TSN protocol can be run over other ethernet speeds also
- Supports MDIO slave and master model as per Clause 22 and Clause 45
- Glitch insertion and detection
- Supports all types of TX and RX errors insertion/detection at each layer.
- Comes with Tx BFM, Rx BFM, and Monitor
- Monitor supports detection of all protocol violations
- Supports Pause frame generation and detection
- Built in coverage analysis
- Callbacks in master and slave for various events
- Status counters for various events in bus
Benefits
- Faster testbench development and more complete verification of Ethernet-TSN designs
- Easy to use command interface simplifies testbench control and configuration of TX and RX
- Simplifies results analysis
- Runs in every major simulation environment
Block Diagram of the Ethernet-TSN Verification IP Verification IP

View Ethernet-TSN Verification IP full description to...
- see the entire Ethernet-TSN Verification IP datasheet
- get in contact with Ethernet-TSN Verification IP Supplier