HMC2 Verification IP

Features

• Compliant with Standard HMC Version 2.0 specification.
• 4GB configuration - 256 memory banks.
• 8GB configuration – 512 memory banks.
• Closed-bank memory architecture.
• Built-in memory controller for each vault – Automatic refresh control over all temperatures.
• Internal ECC data correction.
• Advanced RAS features including data scrubbing.
• Post-assembly repair capability.
• In-field repair for ultimate reliability.
• Up to four 16-lane, full duplex serialized link.
• Up to 320 GB/s effective bandwidth.
• Packet based data/command interface.
• Supports 16,32,48,64,80,96,112,128 and 256 byte references per request.
• Error detection for packets with automatic retry.
• Power Management supported per link.
• Reports various error signals, which can be used to check for any error.
• Provides full control to the user to enable / disable various types of messages.
• Integrates easily in any verification environment.
• Supports full timing models or bus functional models.
• Supports advanced SystemVerilog features like constrained random testing.
• Supports Callback / User Configuration in Monitor, Host and Device Model BFMs.
• Supports wide variety of Dynamic as well as Static Error Injection
• scenarios.
• On the fly protocol checking using protocol check functions,
• static and dynamic assertion.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Monitor,
• Controller and Memory Model BFMs.
• Graphical analyser to show transactions for easy debugging.

Benefits

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure highest levels of quality
• Availability of Compliance & Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity example for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment

Deliverables

• HMC Controller BFM
• HMC Device
• HMC Monitor and Scoreboard
• Test-Bench Configurations
• Test Suite (Available in Source code)
• Basic Protocol Tests
• Directed & Random Tests
• Error Injection Tests
• Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes

Block Diagram of the HMC2 Verification IP Verification IP

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