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Controller Area Network with Flexible Data-Rate (CAN / CAN FD) IP Core
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I2C Master and Slave OVM/UVM Verification IP
The I2C VIP (I²C Inter-Integrated Circuit) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting OVM/UVM, this Master and Slave I2C VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The I2C VIP supports standard, fast and high speed modes of operation and both 7-bit and 10-bit addressing modes. The Master VIP has been interoperability tested with a Slave VIP configuration with the slave VIP was used in successfully verifying a DUT, later silicon proven. The VIP comes with a Bus Monitor for performing key protocol checks and reports errors for non compliance with Philips I2C Specification.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
The I2C VIP supports standard, fast and high speed modes of operation and both 7-bit and 10-bit addressing modes. The Master VIP has been interoperability tested with a Slave VIP configuration with the slave VIP was used in successfully verifying a DUT, later silicon proven. The VIP comes with a Bus Monitor for performing key protocol checks and reports errors for non compliance with Philips I2C Specification.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
Features
- Overview VIP: I2C Master and Slave
- Compliance: UM10204 Rev. 4
- Language: System Verilog
- Methodology: OVM 2.1.1/UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- Technical Specifications
- Each master or slave device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times
- True multi-master including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer
- Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 Kbit/s in the Standard-mode, up to 400 Kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode
- General Call Addressing Support
- Addressing Modes Supported: 7-bit, 10-bit & general call address
- Ability to differentiate between Legal and Illegal Start/Stop conditions
- Wait State Insertion capabilities
- Clock Synchronization of more than two masters connected to the I2C Bus
- Repeated Start Generation Scenarios
- Repeated Start Detection capabilities
- Bus monitor has capability to detect Illegal Start/Stop/Repeated Start Conditions
- Switching between different modes (H-Speed, F-Speed and S-Speed)
Deliverables
- I2C Master or Slave VIP
- Sample Testbench integrated with proven I2C Master or Slave IP
- Sample Scoreboard
- Sample Virtual Sequencer
- VIP User Guide
Block Diagram of the I2C Master and Slave OVM/UVM Verification IP
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