I2C Verification IP provides an smart way to verify the I2C bi-directional two-wire bus. The SmartDV's I2C Verification IP is fully compliant with version 2.1 and 3.0 of the Philip's I2C-Bus Specification and provides the following features.
I2C VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Supports 2.1 and 3.0 I2C Specification.
- Supports standard, fast, and high speed operations.
- Full I2C Master and Slave functionality.
- Operates as a Master, Slave, or both.
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
- Supports all I2C clocking speeds
- 7b/10b configurable slave address
- Compares read data with expected results
- Bus-accurate timing
- Various kind of Master and Slave errors generation
- Glitch monitor and injection.
- Callbacks in master and slave for various events.
- Status counters for various events in bus.
- Faster testbench development and more complete verification of I2C designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of I2C Monitor, Slave, Master.
- Complete regression suite containing all the I2C testcases.
- Examples's showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.