I2S Verification IP provides an smart way to verify the I2S bi-directional two-wire bus. The SmartDV's I2S Verification IP is fully compliant with version 1.1 of the Philip's I2S-Bus Specification and provides the following features.
I2S VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Complies with Philips I2S Specification version 1.1
- Full I2S Master and Slave functionality.
- Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits.
- Supports configurable clock rate.
- Callbacks in master, slave and monitor for user processing of data.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Functional coverage of complete I2S specs.
- I2S Verification IP comes with complete testsuite to test every feature of I2S specification.
- Faster testbench development and more complete verification of I2S designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of master, slave and monitor
- Complete regression suite containing all the I2S testcases.
- Examples's showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.