IEEE 1149.1 (JTAG) Verification IP provides an smart way to verify the IEEE 1149.1 (JTAG) component of a SOC or a ASIC. The SmartDV's JTAG Verification IP works in a highly randomized manner to generate wide range of scenarios for effective verification of DUT.
JTAG VIP includes an extensive test suite covering most of the possible scenarios and detection of protocol violation using a effective protocol-checker.
IEEE 1149.1 (JTAG) VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Supports Jtag protocol standard IEEE 1149.1.
- Supports all the JTAG tap instructions.
- Supports programmable clock frequency of operation.
- Checks for following
- State based rules
- Active Command rules
- Read/Write to Instruction and data register Rules.
- Supports Instruction register and data register of size up to 64 bits.
- Proficiency to extend with user defined instructions and registers.
- Supports constraints Randomization.
- Status counters for various events on bus.
- Supports callbacks for user to define custom instruction decoder.
- Supports callbacks for user to get callback on each state of TAP controller.
- Support all types of timing and protocol violation detection.
- Notifies the testbench of significant events such as transactions, warnings, timing and Protocol violations.
- Functional coverage for checking all possible stimulus checking.
- Has support for reading BSDL file
- Faster testbench development and more complete verification of JTAG designs.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of master, slave and monitor.
- Complete regression suite containing all the IEEE 1149.1 (JTAG) testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.