Truechip's JESD204B Verification IP provides an effective & efficient way to verify the components(data converters and/or logic devices) connecting with JESD204B link.
Truechip's JESD VIP is fully compliant with standard JESD204B.01 specification from JEDEC standard. This VIP is a light weight VIP with easy plug‐and‐play interface so that there is no hit on the design time.
- Support device subclass0,subclass1 and subclass2.
- Supports serial data rate up to 12.5 Gbps.
- Transmission of initial lane alignment sequence and alignment character.
- Supports device class types‐ NMCDA‐SL, NMCDA‐ML, MCDASL, MCDA‐ML.
- Supports combining and non‐combining of SYNC~ signal.
- Supports frame alignment monitoring and correction.
- Supports lane alignment monitoring and correction.
- Supports mechanism for achieving repeatable, programmable deterministic latency across link.
- Supports up to 32 lanes.
- Supports multiple samples per converter per frame cycle.
- Scrambler can be enable or disable.
- Supports error injection and detection in 8b/10 encoder/decoder.
- Supports functional bus coverage and configuration coverage.
- Supports comprehensive compliance test suit, Constraint random test cases and error injection test cases for verification.
- Supports strong protocol monitoring.
- Supports transaction logger for detail description of bus activity.
- Supports bus assertions.
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest level of quality.
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Transmitter and Receiver agent
- Monitor and Scoreboard agent
- Test environment and test suit
- Basic and directed protocol tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration guide, user manual, release notes, ppt for integration of User’s DUT in VIP environment and integration of VIP in user’s Soc environment.
Block Diagram of the JESD204B Verification IP Verification IP