JESD204 (Serial Interface for Data Convertors) is the serial communication protocol developed used with ADC and DAC. JESD204 VIP can be used to verify transmitter or Receiver device following the JESD204 basic protocol as defined in JESD204. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
JESD204 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Follows JESD204A and JESD204B specification
- Support Transmitter and Receiver Mode
- Support up to 32 lanes
- Support 32bit data width per converter
- Support up to 32 converters per transmitter & receiver BFM.
- Support disparity & invalid code insertion in 8b/10b.
- Status counters for various events on bus.
- Supports scrambler as in JESD204 specification
- Support on the fly generation of data.
- Detects and reports the following errors.
- Invalid K character
- Invalid control character
- Supports constraints Randomization.
- Built in functional coverage analysis.
- Callbacks in Transmitter and Receiver for various events
- Faster testbench development and more complete verification of JESD204 designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the JESD204 testcases.
- Examples's showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.