The JEDEC LPDDR4 VIP (JESD209-4) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this LPDDR4 VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The LPDDR4 VIP has extensive constrained-random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance. Pre-defined coverage bins enable easier extension and coverage collection.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
- VIP: LPDDR4
- Compliance: JEDEC JESD209-4
- Language: System Verilog
- Methodology: UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- Technical Specifications
- Single data rate architecture for command and address
- All control and address latched at rising edge of the clock
- Double data rate architecture for data Bus;
- Two data accesses per clock cycle
- Differential clock inputs
- DMI pin support for write data masking and DBIdc functionality
- Programmable RL (Read Latency) and WL (Write Latency)
- Auto refresh and self refresh supported
- All bank auto refresh and directed per bank auto refresh supported
- Auto TCSR (Temperature Compensated Self Refresh)
- LPDDR4 VIP
- Sample Testbench
- Sample Scoreboard
- sample Virtual Sequencer
- VIP User Guide
Block Diagram of the LPDDR4 UVM Verification IP Verification IP