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MIPI C-PHY UVM Verification IP
The MIPI C-PHY VIP is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this C-PHY VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
This UVM VIP has extensive constrained random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance to MIPI standard for C-PHY specification 1.0. Pre-defined coverage bins enable easier extension and coverage collection. The VIP has been verified for protocol compliance using asureSIGN, TVS’ in-house Requirements tracking tool.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
This UVM VIP has extensive constrained random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance to MIPI standard for C-PHY specification 1.0. Pre-defined coverage bins enable easier extension and coverage collection. The VIP has been verified for protocol compliance using asureSIGN, TVS’ in-house Requirements tracking tool.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
Features
- Overview
- VIP: MIPI C-PHY
- Compliance: MIPI 1.0 Specification
- Language: System Verilog
- Methodology: UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa
- Technical Specifications
- Transmission error generation and detection
- Detection of all timeouts
- Injection of various timeout errors
- Parallel Peripheral Interface (PPI)
- Short and long packets
- High-speed and low-power packet transmission and reception
- Uni- and bi-directional communication
Deliverables
- MIPI C-PHY VIP
- Sample Testbench
- Sample Virtual Sequencer
- Sample Scoreboard
- VIP User Guide
Block Diagram of the MIPI C-PHY UVM Verification IP Verification IP
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