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MIPI D-PHY UVM Verification IP
The MIPI D-PHY VIP is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this D-PHY VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
This UVM VIP has extensive constrained-random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance for Host as wells as Peripherals. Pre-defined coverage bins enable easier extension and coverage collection.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
This UVM VIP has extensive constrained-random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance for Host as wells as Peripherals. Pre-defined coverage bins enable easier extension and coverage collection.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
Features
- Overview
- VIP: MIPI D-PHY
- Compliance: MIPI 1.00.00 Specification
- Language: System Verilog
- Methodology: UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa
- Technical Specifications
- One or more differential High-speed functions including differential transmitter HS-TX and differential receiver HS-RX
- One or More differential Low-Power functions including differential transmitter LP-TX, differential receiver LP-RX, Low-Power Contention-Detectors (LP-CD)
- Correlation between High-speed and Low-power functions
- Two Types of Data Lanes (Bi-directional and Unidirectional)
- Single or Multiple Data Lanes
- Supported types of Reverse communication (per Lane)
- Functionality supported by Escape mode (for each direction per Lane)
- Data transmission can be with 8-bit raw data (default) or using 8b9b encoded symbol
- Data shall be serialized in the transmitting PHR and de-serialized in the receiving PHY
- Support for different Lane states and Line levels
- Support for different operating modes
- Bi-directional data lane turnaround
- Bi-directional control
- Support for detecting protocol errors and contention
Deliverables
- MIPI D-PHY VIP
- Sample Testbench
- Sample Virtual Sequencer
- Sample Scoreboard
- VIP User Guide
Block Diagram of the MIPI D-PHY UVM Verification IP Verification IP
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