Truechip's MIPI DPHY Verification IP provides an effective & efficient way to verify the components interfacing with MIPI D‐PHY interface of an IP or SoC.
Truechip's MIPI D‐PHY VIP is fully compliant with MIPI Alliance Specification for D‐PHY Version 1.2. This VIP is a light weight VIP with easy plug‐and‐play interface so that there is no hit on the design cycle time.
- Compliant to MIPI DPHY Specification Version 1.2 with PPI
- Supports high speed, Escape and Low power control mode.
- Supports continuous and non continuous clock behaviour.
- Supports RAW as well as 8b/9b encoding.
- Supports Special symbols like EOT, Protocol marker, Idle1,Idle2 in case of 8b9b line encoding.
- Supports for different line states and line levels.
- Configurable numbers of Data lanes.
- Bi-directional data lane turnaround.
- Supported different types of reverse communication.
- Supports configurable control on timing parameters.
- Supports generation and identification of different error scenarios (SoT Error, SoT Sync Error,EoT Sync Error,
- Escape Entry Command Error, LP Transmission Sync Error,
- False Control Error).
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions, static and dynamic assertion.
- Built in Coverage analysis
- Provides a comprehensive user API (callbacks) in Master and Slave.
- Graphical analyser to show transactions for easy debugging.
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of Conformance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment.
- MIPI DPHY Master/Slave Phy BFM/Agent
- MIPI DPHY Monitor and Score board
- MIPI DPHY PPI Monitor
- Testbench Configurations
- Test Suite (Available in Source code) :
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Coverage Tests
- Compliance Tests
- Integration Guide, User Manual and Release Notes
Block Diagram of the MIPI D-PHY Verification IP Verification IP