MIPI HSI Verification IP provides an smart way to verify the MIPI HSI uni-directional two-wire bus. The SmartDV's MIPI HSI Verification IP is fully compliant with version 1.01 MIPI Alliance specification for serial Interface and provides the following features.
MIPI HSI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Supports 1.01 MIPI HSI Specification.
- Full MIPI HSI Tx and Rx functionality.
- Monitor,Detects and notifies the testbench of all protocol and timing errors.
- Supports all data flow types
- Synchronized data flow
- Pipelined data flow
- Receiver real time data flow
- Supports all transmission modes
- Stream transmission mode
- Frame transmission mode
- Supports wake signal functionality
- Various kinds of error generation and detection
- Missed clock cycles in synchronized data flow
- Missed clock cycles in pipelined data flow
- Additional clock cycles in stream transmision mode with synchronized data flow
- Additional clock cycles in frame transmission mode with synchronized data flow
- Additional clock cycles in frame transmission mode with pipelined data flow
- Incomplete frame transmission
- Unexpected bits transmitted after frame reception is completed
- Incomplete frame transmission support
- Status counters for various events in bus.
- Callbacks in node transmitter, receiver and monitor for user processing of data.
- MIPI HSI Verification IP comes with complete test suite to test every feature of MIPI HSI specification.
- Functional coverage for complete MIPI HSI features
- Faster testbench development and more complete verification of MIPI HSI designs.
- Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of MIPI HSI Monitor,Rx,Tx.
- Complete regression suite containing all the MIPI HSI testcases.
- Examples's showing how to connect various components, and usage of Tx,Rx and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.