NVM Express Verification IP (VIP)

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.

Product Highlights
- First VIP to support NVM Express
- Part of a complete PCI Express solution including: PCI Express Gen3, PCI Express Gen2, NVM Express, Mobile PCI Express, SR-IOV, MR-IOV
- Supports the latest specification ECNs

• see the entire NVM Express Verification IP (VIP) datasheet
• get in contact with NVM Express Verification IP (VIP) Supplier