OpenCores Wishbone B3 Verification IP provides an smart way to verify the OpenCores Wishbone B3 component of a SOC or a ASIC. The SmartDV's OpenCores Wishbone B3 Verification IP is fully compliant with standard OpenCores Wishbone B3 Specification and provides the following features.
OpenCores Wishbone B3 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Compliant to OpenCores Wishbone B3 Protocol.
- Support for all types of Wishbone devices
- Support for programmable wait states.
- Support for programmable Retry insertion.
- Support for programmable Error insertion.
- Configurable transfer size for read and write transactions.
- Support for linear,Fixed and Wrap burst sizes.
- Flexibility to send completely configured data.
- Ability to inject errors during data transfer.
- On-the-fly protocol and data checking.
- Monitor, Detects and notifies the testbench of all protocol errors.
- Supports constraints Randomization.
- Status counters for various events on bus.
- Callbacks in master, slave and monitor for various events.
- WB Verification IP comes with complete testsuite to test every feature of WB B3 specification.
- Functional coverage for complete WB B3 features.
- Faster testbench development and more complete verification of OpenCores Wishbone B3 designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the OpenCores Wishbone B3 testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.