Integrated and Verified with Xilinx UltraScale Kintex PCIE Gen3 Integrated Core, V3.1 (8 lanes). Both PIPE and serial interfaces
The Lite version of PCIE-VR is for FPGA designers who need to verify DMA and other sophisticated features before downloading the bit streams. Debugging FPGA in the lab is very time consuming. PCIE-VR Lite can be used as a full functional root complex, bridge, or end point. You will know for sure your design works before going to the lab.
Not only you can integrate PCIE-VR Lite onto existing test bench in a few hours but also choose your favorite languages, either Verilog, System Verilog, or C, to configure your design. You can use PCIE-VR Lite to replace any simplified root complex and/or the IP core on the test bench. The reason to replace the IP core on the test bench is to speed up the simulation in many folds.