PCIE Verification IP provides an smart way to verify the PCIE bi-directional bus. The SmartDV's PCIE Verification IP is fully compliant with version 1.0/2.0/3.0 of the PCIE Specification and provides the following features.
PCIE VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Supports PCIE Express specs 1.0/2.0/3.0.
- Supports PIPE, Serial, PCS/PMA, and serdes interface.
- Supports Full link speed and width negotiation up to 32 Lanes.
- Supports Automated Error Injections at all layers.
- Supports Checkers verify protocol timing checks and functional accuracy at each layer.
- Supports Queuing for 8 VCs with configurable depth.
- Supports Configurable TC to VC queue mapping.
- Supports for multiple Requestor / Completer applications, including user supplied applications.
- Supports User interface for direct TLP queuing and receipt.
- Supports Checks all TLPs for correct formation of headers, prefixes, and ECRC.
- Supports Full DL state machines.
- Supports Checks all framing, LCRC, and lane rules.
- Supports Check all DLLP fields and formatting.
- Supports Interface to send / receive user defined DLLPs.
- Supports ASPM and Software controlled Power Management.
- Supports Automated Error Injections and checking.
- Supports Full LTSSM state machine.
- Supports SERDES model with digital clock recovery.
- Supports Speed and Link Width negotiation.
- Supports Upconfigure, polarity inversion, and lane-to-lane skew.
- Supports Configurable Spread Spectrum Clocking (SSC).
- Supports Gen 1 & 2 PCS, 8b/10b encoding.
- Supports Gen 3 128/130 encoding.
- Supports Configurable timers and timeouts.
- Callbacks in Root complex,End point and monitor for user processing of data.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- PCI Express Verification IP comes with complete testsuite to test every feature of PCI Express specification.
- Supports scoreboard checking
- Built-in monitors for protocol checking, including a global bus monitor.
- Functional coverage to cover all functionality of PCIE Root complex and End point.
- Support for multiple instantiations to create complex verification environment.
- Faster testbench development and more complete verification of PCI Express designs.
- Easy to use command interface simplifies testbench control and configuration of Root complex and End point.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of PCIE Monitor and BFM.
- Complete regression suite containing all the PCIE testcases to certify PCI Express Root complex and End point.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.