The Simulation VIP for PCIe Gen4 is ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Cadence Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- Part of a complete PCI Express solution including: PCI Express Gen4, PCIe Gen3, PCIe Gen2, NVM Express, Mobile PCI Express, SR-IOV, MR-IOV
- Provide support for Gen4 equalization testing
- Supports x1, x2, x4, x8, x12, x16, and x32 lanes
- Supports the latest engineering change notices (ECNs)
- Speed negotiation and operation at 16GT/s