The PCIe EP VIP (End Point) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this PCIe EP VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The PCIe EP VIP comes with a Bus Monitor for performing all protocol checks. The monitor performs protocol checks and reports errors for non-compliance with PCIe Specification reference.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
- Overview VIP: PCIe EP (End Point)
- Compliance: PCI Express Base 2.1 Spec
- Language: System Verilog, C or C++
- Methodology: UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- Technical Specifications
- Independently controlled egress, ingress traffic, and support for all types of packets
- PCIe and legacy interrupt support
- Gen1 and Gen2 support with optional top speed as Gen1
- Support for Multiple VCs and Multiple TCs
- RAL model for all configuration space registers with back door access
- Flow Control checks and ordering rule monitors
- Full set DLLP Support
- DL Control and Management state machine with FC initialization
- Configurable ACK frequency, FC update frequency and update timer
- Independent LTSSM Monitor
- Auto speed negotiations
- ASPM and PCIEPM support
- Complete Ordered Set support
- Compliance and Loopback mode support
- Highly Flexible, Independent and Configurable PCIE VIP in EP mode.
- Some layers if the VIP are synthesizable.
- Can be used on Emulation platform as well.
- PCIe EP VIP
- Interface to software above transaction layer
- Traffic generator functions for SoC level verification
- Sample Testbench integrated with VIP
- Sample Virtual Sequencer
- VIP User Guide
Block Diagram of the PCIe End Point UVM Verification IP