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PCIe Root Complex Verification IP
The PCIe RC VIP (PCI Express Root Complex) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this PCIe Root Complex VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The PCIe RC VIP comes with a Bus Monitor for performing all protocol checks. The monitor performs protocol checks and reports errors for non-compliance with PCIe Specification reference.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
The PCIe RC VIP comes with a Bus Monitor for performing all protocol checks. The monitor performs protocol checks and reports errors for non-compliance with PCIe Specification reference.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
Features
- Overview VIP: PCIe RC (Root Complex)
- Compliance: PCI Express Base 2.1 Spec
- Language: System Verilog, C or C++
- Methodology: UVM/eRM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- Technical Specifications
- Independently controlled egress, ingress traffic, and support for all types of packets
- Configurable Enumeration sequence support
- PCIe and legacy interrupt support
- Gen1 and Gen2 support with optional top speed as Gen1
- Multiple VCs, Multiple TCs and TC-VC mapping support
- Flow Control checks and ordering rule monitors
- Full set DLLP Support
- DL Control and Management state machine with FC initialization
- Configurable ACK frequency, FC update frequency and update timer
- Independent LTSSM Monitor
- Auto speed negotiations
- ASPM and PCIEPM support
- Complete Ordered Set support
- Compliance and Loopback mode support
Deliverables
- VIP user Guide
- PCIE VIP - RC Mode
- Interface to software above transaction layer.
- Traffic generator functions for SoC level verification
- Sample Testbench Integrated with VIP
- Sample Virtual Sequencer
Block Diagram of the PCIe Root Complex Verification IP Verification IP
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