Questa Verification IP Ethernet Family supports all Ethernet speeds for providing complete verification solution for design containing Ethernet interfaces. Build upon native System Verilog and UVM, Ethernet QVIP Family provides bus functional model (BFM) with complete functionality on latest specification for all Ethernet use models. Ethernet QVIP Family comes with support for all kind packets/stimulus over Ethernet interface ensuring extensive coverage of verification scenarios and exhaustive checking with inbuilt assertion checks. Architected for ease-of-use, QVIP is easy to integrated in all test benches in minimal time enabling user for productive verification quickly. QVIP is well integrated with all Mentor functional verification tools and enabled verification on all platforms ensuring fast and complete verification closure. The QVIP supports on all major simulators(Questasim, VCS and Incisive) and methodologies(UVM). The Ethernet QVIP family enables verification of ethernet interfaces in various use models:
Ã¢ÂÂ¾Q,O,SGMII and RMII support(with preemption)
Ã¢ÂÂ¾Application support like Data security and Time stamping
The Ethernet QVIP Family is compatible IEEE 802.3 Ethernet standards, draft specification, consortium specifications and various other standards popular in Industry.