Questa VIP Family for DRAM

Questa Verification IP Family for DRAM supports all DRAM speeds, including leading edge DDR5 and LPDDR5 and provides a complete verification solution for designs containing SDRAM devices. Built upon native System Verilog (with and without UVM architecture support), QVIP Family for DRAM provides bus functional models (BFM) with complete functionality on the latest specifications for all DRAM use models. It provides easy-to-integrate modules and easy configurability to various vendor part numbers. QVIP Family for DRAM comes with support for all kinds of transactions over DRAM interfaces, ensuring extensive coverage of verification scenarios and exhaustive checking with built-in assertion checks. Architected for ease-of-use, QVIP is easy to integrate in all test benches in minimal time, quickly enabling productive verification. QVIP is integrated with all Siemens EDA functional verification tools and enables verification on all platforms, ensuring fast and complete verification closure. QVIP supports on all major simulators (Questa Sim, VCS, and Incisive) and methodologies (UVM). The QVIP Family for DRAM enables verification of DRAM interfaces as Memory Devices and also in monitor mode. The DRAM QVIP Family is compatible with the latest JEDEC standards.

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