The VITAL FM22L16 behavioral model is fully compliant to RAMTRON FM22L16, 4Mbit F-RAM Memory, Rev, 1.2/Dec.2007 Specification.
The FM22L16 is a 256Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory.
In-system operation of the FM22L16 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM22L16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of a SRAM.
The VITAL FM22L16 behavioral model completely emulates all aspects of real component behavior. This implies complete functionality, all desired relations between input signals (setup/hold , pulse with, etc.) and all delays between inputs and outputs.
The code is written in Verilog HDL and the model is highly portable across the range of simulators and operating systems, but it is tested and completely proven with Candence’s NCSim and Mentor’s ModelSim simulators.
- VHDL’93, Verilog and VITAL’2000 compliant
- Required VITAL’2000 library for correct compilation
- Timing backannotation by means of an SDF files
- Tested on and compatible with Candence’s NCSim and Mentor’s ModelSim Support boardlevel simulation
- Models are written at a behavioral level, do not reveal intellectual property, and are not synthesizable
- Easy to use
- Simplifies design verification process
- Reduces development costs
- Speeds time-to-market with new SoCs
- Standard-based for fast, easy integration
- VITAL Verilog code of the model
- FTM and SDF files
- Memory preload file
- Verilog testbench codes
- Testcases package file
- Testbench structure and testcase description documents