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SERDES Serializer-Deserializer Verification IP
The SERDES-VR Verification IP is providing effective way to verify serdes module functionality. Serial, eight-bit, ten-bit encoded, sixteen-bit, and twenty-bit interfaces are provided to device under test. Various range of protocols are supported including PCI-Express, SATA, Ethernet XAUI/XGXS, 10/100/1000 SGMII, 1000BaseX, Fibre Channel, Sonet, Infiniband, and so on.
Features
- Receive Features
- Clock recovery from the serial data signal
- Comma detection and word alignment
- Word synchronization status notification
- Electric idle state detection
- Code error and disparity error indication
- Data and K-character indication to design under test
- Loopback incoming data to transmit line
- Dynamic rate adjustment as in PCI-Express 2.0
- Transmit Features
- 8b/10b encoding and error injection such as code/disparity anomaly
- Jitter insertion in serial line
- Electric idle state assertion
- Invalid code or disparity word transmission for error injection
- Dynamic clock rate change as in PCI-Express 2.0
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