Serial flash memory model is the serial synchronous communication protocol based Flash memory model, supporting all major Serial flash memory vendors. Serial Flash memory model can be used to verify serial flash controller in SOC. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
Serial Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Support controller and memory model Mode
- Supports 3-wire,4-wire interface
- Supports baud rate selection
- Supports internal clock division check.
- Supports on the fly generation of data.
- Supports backdoor initilization of data.
- Supports constraints Randomization.
- Built in functional coverage analysis.
- Supports Callbacks in controller, memory model and monitor for modifying, and sampling data/cmd on bus.
- Faster testbench development and more complete verification of serial flash controller designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of controller, memory model and monitor.
- Complete regression suite containing all the serial flash memory testcases.
- Examples's showing how to connect various components, and usage of controller, serial flash model and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.