Mature and highly capable compliance verification solution.
ncorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the Ethernet Base-T1 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, the VIP for Base-T1 Ethernet helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Base-T1 Ethernet runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
The VIP for Base-T1 Ethernet enables verification of Ethernet interfaces in standalone, partial-stack, and full-stack mode for speeds of 10Mbps, 100Mbps, and 1000Mbps:
Supported specifications: IEEE specifications of 802.3bw-2015, 802.3bp-2016, and 802.3cg-2019.