Simulation VIP for TileLink
The TileLink protocol is a standard of the RISC-V Foundation® designed for RISC-V processors. TileLink is a chip-scale interconnect standard providing multiple managers with coherent memory-mapped access to memory and other subordinate devices. TileLink is designed for use in a SoC to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complex devices, using a fast-scalable interconnect providing both low-latency and high-throughput transfers.
Supported specification: TileLink specification versions 1.7.1 and 1.8.
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