SMBus Verification IP provides an smart way to verify the SMBus bi-directional two-wire bus. The SmartDV's SMBus Verification IP is fully compliant with version 2.0 of the SMBus Specification and provides the following features.
SMBUS VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Supports SMBus specification version 2.0
- Supports all SMBus device types: Master, Slave
- Supports all SMBus command protocols
- Supports packet error checking
- Supports ARP sequence
- Performs error injection
- Generates and handles glitches generating on both SMBDAT and SMBCLK lines
- Supports timeouts forcing and handling
- Supports scoreboard checking
- Built-in monitors for protocol checking, including a global bus monitor
- Built-in coverage analysis for all transactions types
- Support for multiple instantiations to create complex verification environment
- Faster testbench development and more complete verification of SMBUS designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of SMBUS Monitor and BFM.
- Complete regression suite containing all the SMBUS testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.