The SPI VIP (Serial Packet Interface) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this SPI VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The SPI VIP provides capability to communicate over SPI bus with the SPI transactor comprising a synthesizable hardware component written in System Verilog and a software part written in C++ and System Verilog. The VIP comes with a UVM Monitor for checking the conformance of the design with the technical specifications, performing the protocol checks and reporting compliance errors.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.