SPI/FRAM Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/SPANSION_FLASH Verification IP is fully compliant with SPI Block Guide V04.01 of the Motorola's M68HC11 user manual rev 5.0 SPI-Bus Specification and FM25L512 512Kb FRAM Serial 3V Memory Specification and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
- Follows FRAM basic specification as defined in FM25L512 512Kb FRAM Serial 3V Memory
- Support Master and Slave Mode
- Supports data width of 8 bit
- Supports bus width 1 bit and 4 bit
- Support baud rate selection
- Supports standard, fast, and high speed operations.
- Support internal clock division check.
- Supports Clock Polarity and Clock Phase selections.
- Support single and burst transfer mode.
- Support on the fly generation of data.
- Supports constraints Randomization.
- Glitch insertion and detection
- Built in functional coverage analysis.
- Status counters for various events on bus.
- Supports single,dual bus width operation
- Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on Spansion SPI Flash.
- SPI/FRAM Slave can be configured as standard device or can use FIFO for data passing.
- Master contains rich set of commands for both standard device and FIFO model mode.
- Faster testbench development and more complete verification of SPI/FRAM designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the SPI/FRAM testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.