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Synthesizable DDR4 Bus Functional Model
The EasyIC synthesizable DDR4 model is a fully functional, configurable, and cycle-accurate model based on the JESD79-4 JEDEC standard that can be targeted to a range of emulation systems. The synthesizable DDR4 model enables the user to extensively debug their device in simulation and then conduct intensive validation in the emulation environment or in FPGA.
Features
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
- Fully synthesizable SystemVerilog/Verilog RTL
- Full command interpreter
- Flexible configuration sizes
- Supports N*8 and N*4 bit data widths
- Configurable memory size
- Read and Write leveling support
- Backdoor memory interface
- Full initialization and command sequence monitoring
- Power down entry/exit and maximum power saving mode entry/exit monitor
- Independent bank state verification
- Auto/self-refresh monitoring
- Refresh monitoring
- Synthesizable protocol and timing checks
- Readable trace log to debug and analyze memory transactions
- Error flag/status for simple error monitoring
- Checks can be enabled or disabled individually or by group
- Targeted for simulation platforms (Cadence Incisive, Synopsys VCS)
- Targeted for FPGA based systems (Xilinx/Altera) and ARM integrator
- Targeted for emulation systems (Cadence Palladium, Cadence Protium, Synopsys Zebu, Synopsys HAPS, Mentor V-Station)
Benefits
- Full Verilog RTL available
- Fully functional model for simulation emulation and FPGA environments
- Highly configurable
- Easy to use (comprehensive user guide)
- Wide range of protocol and timing checks
- Flexible configurations
Deliverables
- Full RTL synthesizable code that can be used by a customer in any number of projects.
- Full documentation of the product
- Synthesizable sanity testbench along with the RTL enabling the user to check without using debugger, the correct instantiation & configuration of the BFM
- Full support based on yearly maintenance
- Also available on request:
- Full verification environment for BFMs coded in SystemVerilog using UVM methodology and full Verification specification
- Xilinx MIG-ready BFM version including the Dispatcher Bridgethat allows multiple BFMs to share a single MIG & Physical DDR
View Synthesizable DDR4 Bus Functional Model full description to...
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