TS5 Verification IP
TS5 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Features
- Implemented in native OpenVera, Verilog, SystemC and SystemVerilog.
- Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
- Supports JEDEC TS5 specifications.
- Full TS5 Master and Slave functionality.
- Supports all the TS5 commands as per the specs.
- Supports two wire bus serial interface.
- Supports up to 15 MHz transfer rate.
- Supports I2C & I2CXM operation modes.
- Supports two unique device addresses selected by SA pin.
- Supports start, repeat start and stop for all possible transfers.
- Supports START byte generation and handling.
- Supports Master/Slave arbitration and clock synchronization.
- Supports glitch insertion and detection.
- Supports insertion of wait states by Slave and Master.
- Supports bus reset.
- Supports in-band interrupts.
- Supports parity error check.
- Supports device read address pointer mode.
- Supports error handling while PEC enabled/disabled.
- Write Command
- Read Command
- Supports packet error check.
- Supports insertion of errors
- Random write NACK insertion by Slave.
- Glitch insertion on data at various windows.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Callbacks in Master and Slave for various events.
- Status counters for various events in bus.
- Functional coverage of complete TS5 specs.
- TS5 Verification IP comes with complete testsuite to test every feature of TS5 specification.
Benefits
- Faster testbench development and more complete verification of TS5 designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
Deliverables
- Complete regression suite containing all the TS5 testcases to certify TS5 Master/Slave device.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Block Diagram of the TS5 Verification IP Verification IP

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