Silicon Interfaces’ UART eVC is a fully documented, off the shelf component for Verisity’s Specman EliteTM functional verification environment.
At the heart of every asynchronous serial system is the Universal Asynchronous Receiver/Transmitter (UART). The UART is responsible for implementing the asynchronous communication process as both a transmitter and a receiver (both encoding and decoding data frames). The UART not only controls the transfer of data, but the speed at which communication takes place.
The UART eVC is designed to have generation of data bits and testing of output data according to protocol. It also generates and tests data for error condition. It handles all the three modes: FIFO mode, Auto flow mode and Loop-back mode.
- Fully compliant with the UART specifications.
- Supports transmission interface on one side & reception on other side.
- Protocol Compliance checking.
- Generates the stimulus compliant to transmission interface and reception interface.
- Provides monitoring of signals and data in transmit and receive directions.
- Provides stop bits error notification.
- Provides parity error notification.
- Provides break error notification.
- Provides monitoring of signals and timings for reset, FIFO, Autoflow and Loopback mode
- Generates different number of bits percharacter and checks for it.
- Generates different number of stop bits and checks for it
- Generates odd, even and no parity and checks for it.
- Provides the coverage information
- HDL independent.
- eVCs provide major increase in the productivity and higher quality products. Verification environment including stimulus generation, checking, monitoring and functional coverage.
- It verifies designs that include UART. This eVC accurately verifies and ensures that the particular UART is satisfying the protocol. It includes nunber of bits per character, number of stop bits per character, parity and break control.
- Vera Source
- Complete - Test environment
- Verification Components
- Reference Manual