The UART VIP (Universal Asynchronous Receiver/Transmitter) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this UART VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The UART VIP master supports UART and UART16550 modes and was used in successfully verifying a DUT and later silicon proven. The VIP comes with a Bus Monitor that performs protocol checks and reports errors for non compliance with National Semiconductors UART Specification.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by TVS and successfully deployed by leading SoC companies around the world.
TVS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
- VIP: UART
- Compliance: National Semiconductor PC16550D
- Language: System Verilog
- Methodology: UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
- The UART VIP supports:
- Master mode and slave mode
- Independently controlled transmit, receive, line status, and data set interrupts
- Programmable baud generator divides any input clock by 1 to (2^16 – 1) and generates the 16 clock
- Independent receiver clock input
- MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
- Fully programmable serial-interface
- 5-, 6-, 7-, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- 1-, 1(/2-, or 2-stop bit generation
- Baud generation (DC to 1.5M baud)
- False start bit detection
- Complete status reporting capabilities
- TRI-STATE TTL drive for the data and control buses
- Line breaks generation and detection
- Highly Flexible, Independent and Configurable UART VIP
- Proven against Silicon Proven VIP
- Less TAT in integrating into SOC Verification environments
- VIP user Guide
- UART OVM VIP
- Sample Testbench Integrated with proven XILINX UART VIP
- Sample Scoreboard
- Sample Virtual Sequencer
Block Diagram of the UART UVM Verification IP Verification IP