UFS 2.0 Memory Model

The Memory Models for UFS 1.0 are ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Memory Models support the Universal Verification Methodology (UVM) as well as legacy methodologies.

• see the entire UFS 2.0 Memory Model datasheet
• get in contact with UFS 2.0 Memory Model Supplier