Synopsys VC Verification IP (VIP) for Ethernet provides complete support for Ethernet 10/100/1000M/10G/40G and 100G interfaces. With a comprehensive set of protocol, methodology, verification and ease-of-use features, users are able to achieve rapid coverage convergence for their Ethernet-based designs.
- 10/100M, 1G, 10G, 40G, 100G speed support
- MII, RMII, SMII, GMII, RGMII, SGMII, XGMII, XLGMII, CGMII MAC interfaces
- TBI, XSBI, XFBI, XLSBI, CSBI, XAUI, XLAUI and CAUI interfaces
- MDIO clause 22 and clause 45 support
- Data, pause control, VLAN, PPP, PTP 1588, jumbo frames
- Supports transmit and receive of multiple packet types in layers 2/3/4/7
- Options to add proprietary/custom headers and payloads
- IEEE P802.3bj/D3.0 Energy Efficient Ethernet (EEE)
- IEEE P802.3bj/D3.0 100G BASE-R FEC
- Forward error correction, auto-adaptation and auto-negotiation
- Skew insertion and lane reversal
- Dynamic speed switching
- VC VIP Ethernet is integrated with the Protocol Analyzer, a protocol-aware debug environment that enables users to quickly debug protocols by raising the abstraction level and providing easy navigation through layers of the protocol hierarchy.
- VC VIP Ethernet is written entirely in SystemVerilog enabling it to run natively in supported simulators for highest performance.
Block Diagram of the VC Verification IP for Ethernet Verification IP