New Silicon IP
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32-Bit RISC-V Embedded Processor and Subsystem. Maps ARM M-0 to M-4. Optimal PPA.
- 32-bit RISC-V core
- 2-stage pipeline
- Available in many versions
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DisplayPort 1.2a TX PHY targeting 28nm Artix-7
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14-stereo AAC-LC Audio Encoder
- All encoders use the Fraunhofer IIS software
- Configurable output latency useful to synchronize with other sources (up to 8 frames)
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Pulse Per Second (PPS) Clock to PPS core
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DisplayPort 1.4 IP-core
- Compact RTL footprint
- Easy-to-use
- Simple API
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VPU R3.0 on Artix 7 100T
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IP Camera Front End
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Revolutionary vector processor
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Ceva-Waves Bluetooth 5.4 dual mode Baseband Controller
- Compliant with Bluetooth dual mode specification up to version 5.4
- Support all the features including: LE 2Mbps, LE Long Range, LE Advertising Extensions, LE Channel Selection #2, LE
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