Design and evaluation of power-efficient SoCs

Block selection

The ARM926EJ-S processor core was hardened and modeled using the jointly developed ARM-Synopsys Reference Methodology (RM) and Artisan's standard cell library. The CPU memories were generated using Artisan's single-port RAM generator. Synopsys' DesignWare AMBA 2.0 bus and peripheral components were configured and synthesized with Synopsys' CoreConsultant utility to the target TSMC process using Artisan's standard cell library. A custom power supply pad was added to segregate power to each disparate voltage domain.

System integration and synthesis

Timing-critical modules (power/test/reset/clock-control logic) were individually hardened to ensure the targeted performance was attained. The cell coordinates and connectivity netlists for top-level integration were extracted for use in post-route static-timing analysis and system-level scan stitching to allow post-route accur ate static timing analysis and scan stitching with full instance visibility within these hardened modules. Finally, the system was assembled at the top level and synthesized. System-level scan insertion was completed using Synopsys' Design Compiler and DFT Compiler power analysis was completed using Power Compiler.

Place and route

Using Synopsys' Astro, timing-critical blocks and cell macros were placed, the pad ring was created and power nets were prerouted. To ensure proper connections between voltage domains, the level shifters and isolation clamp cells at domain boundaries were pre-placed and pre-routed. The remaining standard cells were placed and optimized using Synopsys' Physical Compiler. Clock trees and high fan-out nets were synthesized and balanced across voltage domains to meet skew and latency requirements. Finally, routing was completed with Astro's crosstalk preventive router.

Timing analysis

After completing global routing, the design parasitics were extracted us ing Synopsys' Star-RCXT, static timing and signal-integrity were analyzed using Synopsys' PrimeTime SI and gate-level simulations were performed in Synopsys' VCS to ensure the design met sign-off requirements. Finally, the design scan coverage was calculated and test patterns were generated using Synopsys' TetraMAX.

The test chip was fabricated and assembled onto a basic evaluation platform for operating system development and power supply control and analysis. The chip was fully functional and operated at the target frequency of 240 megahertz. The independent power domains allowed precise voltage control and current measurement for the CPU subsystem and the RAM. Standard cells and level shifters all operated correctly in the required 0.7-V-to-1.32-V range.

For cache-intensive workloads, both the power consumption and the precise time to process a workload were measured in order to compare and contrast basic dynamic frequency scaling (DFS) with the minimum sustainable voltages determined to support dynamic voltage and frequency scaling (DVFS). The integrated HPM, working with National's Advanced Power Controller (APC), allows product operation at these minimum voltage levels with adaptive voltage scaling (AVS).

The data in Fig. 2 shows that--while DFS is valuable for reducing the average power consumption of the CPU subsystem--it is not a useful technique for reducing task execution energy; consequently, DFS by itself is not an optimal technique for extending the battery life of handheld products.

In contrast, the data presented for DVFS, where both supply voltage and frequency are controlled, shows that this technique can significantly reduce energy consumption. Running at half frequency (120 MHz) reduces the energy requirements to less than 40 percent compared with running at nominal maximum speed. Battery life can be extended where the application software mix allows for such scaling. Today, ARM, National, Synopsys and Artisan are working together to automate and improve this important metho dology.

ARM is developing a Linux operating system port and its ARM IEM software policies are available. These will be evaluated with the National AVS technology for complete system-level power analysis.

National Semiconductor will continue to reduce power consumption and improve energy efficiency in portable devices, taking a system-level approach, with standby and run-time leakage reduction in mobile phone processors, RF energy management, low-power audio and other analog integrated circuits.

Synopsys plans to implement advanced features in multivoltage design within the Galaxy Design Platform to facilitate the integration of critical components--such as level shifters and isolation cells--and the manipulation of voltage islands.

Artisan plans to make its voltage level shifters available for selected standard cell libraries to support designs with multiple voltage domains. Artisan also plans to provide scalable polynomial delay modeling and scalable polynomial power modeling that offers a ccurate timing and power representation with variable supply voltage.

Dynamic and adaptive voltage scaling strategies described here can be deployed to achieve a low-power energy efficient operation by controlling the voltage in conjunction with controlling the operating frequency.

David Flynn is a fellow in the ARM Ltd.'s Research and Development Group. Co-authors are Gordon Mortensen, engineering manager of advanced technology, Portable Power Systems Group, at National Semiconductor Corp.; Pin-Hung Chen, a research and development engineer, DesignWare Amba IP Products, in the Solutions Group at Synopsys Inc.; and Neal Carney, vice president of marketing for Artisan Components Inc.

See related chart The test chip implemented a system architecture for a power-efficient SoC design. Source: Synopsys Inc.

See related chart The test chip power/energy evaluation summarizes the results normalized to the nominal 1.2V operating voltage. Source: Synopsys Inc.