The Cadence® DDR controller and PHY IP can scale up to 3200Mbps, which provides flexibility for designers to easily take advantage of higher performance ...
Synopsys today announced availability of the DesignWare® ARC® HS38 Processor, the latest addition to the ARC HS Family of high-speed processor IP cores. ...
Randy Smith, Interim VP of Marketing, Sonics
This Isn't Your Father's JTAG Anymore
Simplifying SoC Verification by communicating between HVL Env and processor
Use test data to diagnose failed memory
High-Reliability FPGA Designs
Choosing the right A/D converter architecture and IP to meet the latest high speed wireless standards
Cadence Design Systems
Performance analysis of 8-bit pipelined Asynchronous Processor core
Yasha Jyothi M Shirur
BNM Institute of Technology
Security in transit
Tampering with the easy targets