- Via ROM 48KByte IP/Compiler on SMIC 130LL (Oct. 16, 2014)
- ADC + DAC - TowerJazz 0.18u (Oct. 06, 2014)
- Reed Solomon Decoder and Encoder (soft input, hard output) (Oct. 03, 2014)
- USI-T (Oct. 03, 2014)
- ADC & PLL & Video DAC at SMIC 90nm LL process (Sep. 29, 2014)
- NFC tag IP (Sep. 10, 2014)
Synopsys today announced the new DesignWare® Sensor and Control IP Subsystem, a complete hardware and software solution optimized for a wide range of ...
Synopsys today introduced the industry's first USB 3.1 IP solution, consisting of DesignWare® USB 3.1 Device Controller, an IP Virtual Development Kit ...
Cadence today announced the industry's first Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification.
Soft Machines Inc., a Silicon Valley-based semiconductor startup company, today announced the Soft Machines VISC™ architecture. The VISC architecture ...
SMIC and Maxscend Technologies announced that Maxscend Bluetooth RF IP has been silicon proven on SMIC's 55nm Low Leakage (LL) logic process. This IP ...
Kurt Shuler, VP Marketing, Arteris
Achieving 200-400GE network buffer speeds with a serial-memory coprocessor architecture
Selecting an operating system for an embedded application
IC mixed-mode verification: The Sandwiched-SPICE approach
Multiple clock domain SoCs: Verification techniques
The IoT Spurs the Pursuit of Low Power
Understanding Peak Floating-Point Performance Calculations
This Isn't Your Father's JTAG Anymore
Simplifying SoC Verification by communicating between HVL Env and processor