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New Lattice ispClock Family Provides a Standard Clock Distribution Solution Across Multiple Designs
Four Operating Configurations in the ispClock5300S Devices Support Implementation of Multiple Types of Clock Distribution Networks
HILLSBORO, OR -- April 24, 2006 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the first member of its new ispClock™5300S family of in-system programmable, zero-delay, single-ended universal buffer devices, the 12-output ispClock5312S. The E2CMOS-based ispClock5300S devices support programmable clock skew, termination and interface standard support. The ispClock5300S devices support four operating configurations, including Zero-Delay Buffer mode, Combined Zero-Delay and Non-Zero-Delay Fan-out Mode, Dual Fan-out Buffer Mode and Fan-out buffer with output dividers. "Our ispClock5300S device family provides a standard clock distribution solution across multiple designs," said Stan Kopec, Lattice corporate vice president of marketing. “Traditionally, designers have resorted to using unique Zero-Delay Buffer ICs, Fan-out Buffer ICs and Logic Translator ICs for each clock network design. The ispClock5300S family allows each pin to be configured for the necessary functions individually, resulting in a simple programmable solution that can be customized to suit the design requirements of each circuit board. The programmable skew, termination and slew rate features further reduce the design effort and result in both reduced board space and improved manufacturability and reliability,” Kopec concluded. The ispClock5300S devices use three 5-bit on-chip output counters to provide the generation of up to three clocking frequencies derived from one reference. Output clock frequencies can range up to 267 MHz. The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 100 ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70ps and the period jitter is less than 12 ps (rms). The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length. The Universal Fan-out Buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs. The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity. Advantages of the ispClock5300S Devices The Number of Clock Distribution ICs is Reduced – The ispClock5300S devices can integrate multiple types of clock distribution ICs such as Zero-Delay Buffers, Fan-out Buffers and Translators, so designers can easily select the features needed for each individual output pin in their application. In addition, the reference clock input integrates the necessary termination resistors, simplifying interfaces to popular single-ended as well as differential logic interface standards such as LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, Differential HSTL and Differential SSTL at a variety of voltage levels. Clock Network Layout is Simplified by Compensating for Timing Delays Due to Clock Trace Length Differences - Traditionally, clock network designs are constrained to maintain equal clock trace lengths to ensure timing integrity using serpentine patterns to accommodate the extra length clock traces. Because the outputs of the ispClock5300S devices can be skewed precisely in 156 ps increments, designers can route clock patterns more conveniently, and can compensate for the clock edge arrival delay by skewing each output at the device Circuit Board EMI Emission is Reduced by Staggering Clock Edges - To meet strict EMI standards, designers have commonly resorted to using spread spectrum clocks, which intentionally introduce jitter to diffuse peak power emissions due to coincident clock edge across multiple devices. However, the increased jitter in the clock is frequently not desirable. The fine output skew feature of the ispClock5300S devices enables designers to stagger the clock edge in steps of 156 ps, allowing the clocking edge to be spread without introducing jitter, and creating a superior method for EMI emission reduction. PAC-Designer® Software The Lattice Windows-based mixed signal software design tool, PAC-Designer® Version 4.5, provides comprehensive support for the ispClock5312S device. Design configurations can be downloaded quickly via the PC parallel port. This version of the PAC-Designer software can be downloaded for free from www.latticesemi.com Pricing and Availability Prices for the first available device, the ispClock5312S, start at $3.00 in high volume (10KU+) quantities. The ispClock5312S, in a 48-pin TQFP package, is available immediately in both commercial (0oC to +70oC) and industrial (-40oC to +85oC) temperature grades. PACsystemCLK5312S evaluation kits are available through authorized Lattice distributors, or on the Lattice website for $295. The ispClock5308 (8 output device) and ispClock5304 (4 output device) are expected to be introduced in the second half of 2006. About ispClock Devices: Lattice is extending the benefits of integration, in-system programmability and superior performance to clock management. Historically, clock networks have been designed using multiple, simple components -- such as fan-out buffers, clock generators, delay lines, zero delay buffers and frequency synthesizers -- with limited functionality at various levels of the clock hierarchy. Timing errors due to unequal PCB trace lengths have been addressed by using trace length matching through serpentine trace layouts. Trace impedance mismatch has been frequently mitigated by trial and error selection of series resistors. In contrast, ispClock devices are the first products that conveniently and accurately solve the entire clock tree design problem with a single chip. The ispClock devices compensate for timing errors due to different trace length clock nets through a programmable skew feature, match trace impedances with output impedances by programming each output characteristic, and reduce EMI by programming output switching speed or slew rate. This results in board space savings, improved signal integrity, a simpler clock net hierarchy, improved timing convergence and lower cost. About Lattice Semiconductor Lattice Semiconductor Corporation provides the industry’s broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC®) and Programmable Digital Interconnect Devices (ispGDX®). Lattice also offers industry leading SERDES products. Lattice is “Bringing the Best Together” with comprehensive solutions for system design, including an unequaled portfolio of non-volatile programmable devices that deliver instant-on operation, security and “single chip solution” space savings. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com
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