NOR continues to battle NAND flash memory in the handset

Peter DiPaolo, Semiconductor Insights
Jul 12, 2005 (5:00 AM)

With NOR- and NAND-type flash memory jockeying for position, there's considerable debate over whether these technologies will coexist or compete. Semiconductor Insights' recent teardown of the NEC FOMA 900iL handset brings this question to bear. With the progression from 2G to 3G+ handsets over the next few years, handsets are requiring more elegance, which is supported with NOR flash, along with additional storage features, attributed to NAND flash. The 900iL has integrated both flash types into its feature-rich handset, which is dual VoIP and FOMA network capable, and offers video and still-image capabilities.

Note that from the data mined by Semiconductor Insights' Handset Design Win (HDW) subscription service, we see a mix of NOR/NAND combinations. Most of the Japanese high-end handsets use NOR and NAND in their designs, while North American designs have historically leaned towards a NOR-based design.

Will this type of harmony become mainstream, or will the incumbent leaders fight the battle for design wins? Intel and Spansion support NOR, while Samsung and Toshiba support both types. Intel remains committed to its NOR program and believes that NOR is the best solution for the "sweet spot" density in the high-volume, mid-range handset market. On the other hand, Toshiba believes NAND will be the mainstream solution in mid-range and high-end phones due to increasing storage requirements driven by cameras, music, video, and other functionality.

Handset architectures must be sensitive to a range of memory throughput requirements, from low-end handsets through to high-end and video/smart phones. In this scenario, the required memory throughput dictates what combinations of flash (NOR and NAND) and RAM are needed to satisfy the increasing handset complexities. As higher-end applications, video, and general smartphone functions are squeezed into 2.5 and 3G phones, memory throughput can climb from less than 50 Mbytes/s to greater than 150 Mbytes/s. Also, multimedia apps are driving the demand for increasing flash densities.

Where does this put NOR vs. NAND inside the handset? To appreciate the differences, let's look at the handset architectures and operator business models being implemented to understand the requirements and limitations.

The two main architectures for handset memory subsystems are NOR plus RAM and NAND plus RAM, although a combination NOR plus NAND plus RAM is gaining acceptance in high-end phones, to take advantage of the strengths of both NOR and NAND. NOR-based phones use "execute-in-place" (XIP), while the NAND alternative uses "code shadowing."

For each approach, RAM is included for working memory, whether it's SRAM, Pseudo SRAM or DRAM. The essence of XIP, as the name implies, is that code can be executed in place, with some SRAM buffering required. Code-shadowing architectures involve heavy copying of code between the NAND and Mobile SDRAM. XIP is a proven architecture with fast code execution from NOR and no RAM overhead, whereas code shadowing uses a new architecture (both hardware and software), with fast code execution from the DRAM, but resulting in performance issues with RAM overhead and paging slow-down. Power consumption also becomes an issue with code shadowing, compared to XIP, which uses less power during operation.

The limitations and benefits
NAND flash, in general, has its limitations. For example, you can't boot from NAND. In terms of stability, NAND has some issues with bit-flipping, bad blocks, and a limited lifespan. Also, it uses a non-standard interface and requires software management, which can drive up the system cost. Some architectural options can help solve these issues, but there are still other technical implementation tradeoffs needed to resolve the aforementioned concerns.

In the past, NAND flash usage in handsets was limited by the availability of controllers supporting this memory. Today, however, the high-volume baseband chip set vendors support NAND, and others already do so or will shortly. The NAND controller within the baseband chip set handles error correction and software management for wear leveling, and with a small amount of on-chip memory, enables booting from a NAND-based phone.

On the modem side, NAND can't perform random access, and it requires additional DRAM to execute modem instruction code. NAND tends to increase power consumption for reads and adds latency on boot-up. On the other hand, NOR's write and erase power consumption is higher than NAND. Error correction is typically used with NAND, similar to that used with hard drives, and is included on many third-party NAND controllers.

In NAND's defense, the ever-increasing function set in handsets will drive designers to use NAND. Games, general applications, multimedia, heavy data-centric requirements, and the need for a mobile mass-storage medium, puts NAND ahead of NOR. One major benefit of NAND in a handset application is the write speed, and the time required to erase a previous block and write a new one.

One of NOR memory's biggest drawbacks is high density. Although the speed and code execution attributes weigh in NOR's favor, it's still encumbered by its relative lack of density compared to NAND. NOR offers a range of densities from the low end to the "sweet spot" for low to mid-range handsets (128 to 256 Mbits) up to 512 Mbits. NOR can also be stacked to offer gigabit density. However, 512 Mbits is at the high end of what OEMs are using today.

Choosing the right density
NOR flash is ideally positioned for the handset's memory density sweet spot. With the majority of volume sales for mid to low-range phones having density requirements between 32 and 256 Mbits, current NOR components can deliver these densities. Although high-end phones can require upwards of 512 Mbits to 1 Gbit, these devices haven't yet reached volume sales levels that makes this memory density necessary. Also, the business model for high-storage handsets remains unproven in geographies where the handset is bundled with the mobile service by the operator. Additional handset storage has yet to translate into added usage revenues for carriers supplying high-end phones.

One flash vendor's position is that as the transition to volume sales of high-end handsets progresses, NOR flash will be able to keep pace on the density front. This will be made possible by the migration of process nodes from 130 65nm in 2006, which will keep NOR's density competitive.

Alternatively, a second vendor notes that NAND is already making noticeable inroads in the handset market. In 2004, about 15% of MCPs for the handset market incorporated NAND. Most of these added NAND for data storage while retaining NOR for code execution (and RAM for working memory), such as the NEC handset (see the figure)

 

 

This pcb comes right out of an NEC FOMA 900iL handset. It shows Intel's NOR flash memory working in conjunction with Toshiba's NAND flash.

Cohabitation of NOR and NAND
Handset vendors can either choose a preferred strategy and the associated flash that enables the solution, or choose both and let them work together to get the best of both worlds. Read speed and the XIP architecture are reasons that NOR is used to store and run code. Density and faster program and erase speeds (write speeds) are the main reasons that NAND devices are used to store images and content.

There could be a point when code required for communications support becomes too large for NOR to support. This transition from NOR to NAND may occur when the total cost/bit plus the additional overhead costs sway in NAND's favor. Another perspective is that NOR can grow with density demands as handsets evolve in the coming years, eliminating the need for NAND completely.

Right now, NAND still lags NOR in read speed, while NOR is considerably behind NAND in density. Until one technology can bridge the advantage gap offered by the other, there will continue to be cases, such as in the NEC FOMA 900iL handset, where NAND and NOR can, and will, co-exist.

About the author
Peter DiPaolo is a technology manager at Semiconductor Insights. He received his Bachelor of Applied Science in Electrical Engineering from Queen's University in 1997. He can be reached at peterd@semiconductor.com.