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New Products

T2M GmbH
UWB RF Transceiver IP 22nm
MAXVY Technologies Pvt Ltd
MAXVY AVS BUS TARGET IP
TES Electronic Solutions
DC-DC Split-Pi Boost-Buck Converter, 10V up to 30V input voltage, 3.3V output voltage at 200/133mA load current
Viettel Semiconductor Center - Branch of Viettel Group
3GPP LTE Turbo Encoder and Decoder IP Core
Qualitas Semiconductor
UCIe 2.0 PHY for Standard Package (2nm)

Blogs

Microsoft accelerates quantum-safe timeline for adoption by 2029
PQShield
Matthew Stubbs
PQShield
Why crypto-agility requires real governance
PQShield
Johannes Lintzen
PQShield
The Three Phases of AI Adoption
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
Advancing UCIe Performance: Enabling 40G for Next-Generation Multi-Die Designs
Synopsys, Inc.
Manuel Mota
Synopsys, Inc.
Why DACs are so crucial in modern chip design
Agile Analog
Chris Morrison, VP Product Marketing
Agile Analog
India as the Emerging Global Semiconductor GCC Hub
Capgemini Engineering
Capgemini Engineering
TEVIOS Becomes Official Distributor of intoPIX AV Solutions
intoPIX
intoPIX
The quantum countdown: what the new White House EO 14409 means for PQC
PQShield
Matthew Stubbs
PQShield
What the Cyber Resilience Act means for the future of chip design
Arteris
Arteris
Advancing Flash Memory Performance for the Edge AI Era
Sérgio Silva
DDR Verification Challenges in Modern Chip Design
SmartDV Technologies
When does it make sense to move from a monolithic ASIC to a chiplet-based design?
IMEC
By Christopher Hunat & Nidish Gaur
IMEC

Articles

High-Speed SerDes Design: Architecture, Equalization, and CDR Circuits
MosChip Technologies, USA
Vivek Babu Avuri
MosChip Technologies, USA
Architecting the Future: Building Smarter SoCs with RISC-V
Aion Silicon
Paul Martin
Aion Silicon
AI-Accelerated Software Security Vulnerability Discovery: Is Hardware Next?
Arteris
Andreas Kuehlmann, General Manager – Security Solutions
Arteris
7 Ways to Efficiently Scale IP Lifecycle Management
IC Manage
IC Manage
Case Study: Completing CDC sign-off by linking static & dynamic verification – with Real Intent Meridian CDC
Real Intent
Real Intent
Beyond the Firewall: Hardware-Enforced Network Isolation for Critical OT Infrastructure
CetraC
CetraC
Detect, Diagnose, and Debug using Sensors and Functional Monitoring
Siemens EDA
Movellus & Siemens EDA
Siemens EDA
SOS Core: Reliable, High Performance Design Data Management for Semiconductor Engineering Teams
Keysight Technologies
Keysight Technologies
Case Study: Multipolicy SoC Linting Methodology with Real Intent Ascent Lint
Real Intent
Real Intent
Accelerate Your Innovation: Why FPGA System on Modules (SoMs) Are the Strategic Choice
ElectraIC
ElectraIC
Considerations When Architecting Your Next SoC: NoCs with Arteris
Aion Silicon
Piyush Singh, Aion Silicon & Andy Nightingale, Arteris
Aion Silicon
Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight
Francisca Tan, Senior Product Manager, Tessent Embedded Analytics
Siemens Digital Industries Software
Asic Technology
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FPGA and eFPGA Corner
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Today on Design And Reuse

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bullet_arrow  KSIA Welcomes New Domestic Semiconductor Investment Plan - July 6, 2026

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