Design & Reuse
Partner Highlight

New Products

Sofics
High ESD robustness protection for 0.75V / 1.2V / 1.8V / 3.3V / 5V - 8kV HBM & IEC 61000-4-2
WASIELA
NavIC BCH Decoder
Global IP Core Sales
FH-OFDM Modem
Renesas
LVDS I/O Buffer 40/28/22/16/7nm
Quadric
Chimera QC Multi 864 TOPS general purpose NPU

Blogs

How to design secure SoCs, Part V: Data Protection and Encryption
KiviCore
KiviCore
How GF FDX™ and FinFET solutions are powering the next generation of Wi-Fi
Suzanna Chang, Sr. Director, IoT End Market
GlobalFoundries
LPDDR6: A New Standard and Memory Choice for AI Data Center Applications
Cadence Design Systems, Inc.
Frank Ferro
Cadence Design Systems, Inc.
The Role of Data Annotation in Building Autonomous Vehicles
MosChip Technologies, USA
MosChip Technologies, USA
Introducing Cadence's Virtuoso Studio RF: Advancing RF Design for 3D-IC
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
A Deep Dive into AI-Driven Optimization with WiCkeD: The Optimization Powerhouse
Cadence Design Systems, Inc.
Niyati Singh
Cadence Design Systems, Inc.
Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
Alphawave Semi
Tony Chan Carusone
Alphawave Semi
Exploring Alphawave Semi's AlphaCHIP1600-IO Chiplet and its Real-World Applications
Alphawave Semi
Shivi Arora, ASIC IP Solutions, and Sue Hung Fung, Product Line Manager
Alphawave Semi
Encouraging women in the semiconductor sector
Agile Analog
Christelle Faucon, VP Sales
Agile Analog
The Upcoming NPU Shakeout
Quadric
Quadric
Enabling Chiplet Design Through Automation and Integration Solutions
Arteris IP
Andy Nightingale
Arteris IP
How to design secure SoCs Part IV: Runtime Integrity Protection
KiviCore
KiviCore

Articles

Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY
Mixel, Inc.
Michael Nagib, Mixel and Nuno Martins, Xpressphy
Mixel, Inc.
Why RPAs Fall Short in IIoT and How Agentic AI Fills the Gap
MosChip Technologies, USA
Rakesh Nakod
MosChip Technologies, USA
ComputeRAM in AI accelerators: An LLM case study
Synthara
Synthara
RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
By Mr. Shailesh Vasekar (Senior Consultant at VeriFast Technologies)
Transition Fixes in 3nm Multi-Voltage SoC Design
eInfochips, Inc.
Rahul Parmar and Mayursinh Vansadiya
eInfochips, Inc.
Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
Innosilicon Technology Ltd
Innosilicon Technology Ltd
Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC
Menta
Menta
Menta
How to design secure SoCs, Part III: Secure Boot
KiviCore
Kivicore
KiviCore
Automating NoC Design to Tackle Rising SoC Complexity
Arteris IP
Andy Nightingale
Arteris IP
One Platform, Five Libraries: Certus Semiconductor's I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies
Certus Semiconductor
Certus Semiconductor
Fault Management and Design-for-Test Strategies in Network Chip Architectures
Choosing the Right RFIC Design Partner
asicNorth
AsicNorth
asicNorth
Asic Technology
Select your target foundry and technology
FPGA and eFPGA Corner
Select your target vendor and device
Today on Design And Reuse

bullet_arrow  Perceptia Devices Release pPLL08W, best-in-class RF PLL IP in GF22FDX - July 17, 2025

bullet_arrow  Pioneering Performance: How Allegro DVT Is Accelerating AV1 Adoption in SiliconPermalink - July 17, 2025

bullet_arrow  2025 TSMC Technical Talk: Exploring Diverse Paths in Semiconductor Technology - July 17, 2025

bullet_arrow  Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the "One Stop" for Memory Interface Solutions - July 17, 2025

bullet_arrow  New architecture for AI datacentres proposed - July 16, 2025

bullet_arrow  IHP, eMemory and its subsidiary PUFsecurity Break Ground on Open Access to Hardware PUF-based Security IP in Europe - July 16, 2025

Partner Highlight
Latest News Alerts