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Omni Design Technologies, a leading provider of high-performance, ultra-low-power mixed-signal Intellectual Property (IP) solutions, today announced a ... Read

Xilinx today announced it is working with its IP and system integrator ecosystem to provide the industry’s first and only production-ready multimedia ... Read

Arteris IP, a leading provider of system-on-chip (SoC) system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate ... Read

Synopsys today announced a collaboration with TSMC to develop a broad portfolio of Synopsys DesignWare® Interface and Foundation IP on the TSMC N4P process. ... Read

TSMC (TWSE: 2330, NYSE: TSM) today introduced its N4P process, a performance-focused enhancement of the 5-nanometer technology platform. N4P joins the ... Read

Analog Bits will be presenting two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases ... Read

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• Most PPA optimized GUC multi-die interLink (GLink 2.3) 5nm IP tape-out in Oct'21
• Robust transmission, 5Tbps/mm, 0.3pJ/bit
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• Encompasses Arasan's MIPI I3C Host controller, Device Controller and PHY.
• High performance, very low power, and reduced pin counts.
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• Compliant with MIPI I3C latest specifications

• Complete solution for multi-port Ethernet
• 100G to 800G aggregate bandwidth
• Line-rate, fully flexible bandwidth allocation
• Designed for data centers, enterprise & carrier networks

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• By optimizing near threshold voltage operation
• For wearables, hearables, IoT, always-on devices
• Proven silicon on TSMC process
• Selected for EIC Accelerator

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