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New Products

Dolphin Semiconductor
complete measurement subsystem IP for single phase power meteringi in HHGrace 130eF
NTLab
180XFAB_ADC_02 - 10-bit 1-channel 20-100kSPS SAR ADC
eMemory Technology Inc.
NVM EEPROM NeoEE in DBHitek(180nm, 90nm)
AionChip Technologies
Ultra-Low Latency 32Gbps SerDes Phy IP in 22 nm
Deepmentor
DeepLogCore® – Ultra-Low Power, High-Efficiency Vision Edge AI Object Detection Accelerator (CNN/YOLO Optimized)

Blogs

How physical AI and edge AI defined CES 2026 in Las Vegas
Arm Inc.
A Chip Designer’s Perspective of RISC-V Traps
Maven Silicon
P R Sivakumar, Founder and CEO
Maven Silicon
Securing AI at Its Core: Why Protection Must Start at the Silicon Level
Synopsys, Inc.
Dana Neustadter, Vincent van der Leest
Synopsys, Inc.
Transforming Data Management in EDA: How Keysight SOS Prepares You for the AI Era
Keysight Technologies
María Castillo
Keysight Technologies
BOS Semiconductors and Rambus: Securing the Future of Automotive AI
Rambus, Inc.
Raj Uppala
Rambus, Inc.
Top Tech Trends 2026: seven trends in the semiconductor sector for 2026
STMicroelectronics
STMicroelectronics
RISC-V and AI/ML redefining the future of Edge Computing
MosChip Technologies, USA
Ambuj Nandanwar
MosChip Technologies, USA
JESD204 Frame Mapping explained from converter samples to lanes
Chip Interfaces ApS
Piotr Koziuk
Chip Interfaces ApS
Starting the new year with a fresh focus on novel analog IP
Agile Analog
Krishna Anne, CEO
Agile Analog
Why Chiplets Are Key to Next-Gen Software-defined Vehicles
Arm Ltd.
Arm Ltd.
Top 5 trends you can expect from CES 2026 in Las Vegas
Arm Ltd.
Arm Editorial Team
Arm Ltd.
Maven Silicon & iHUB DivyaSampark, IIT Roorkee Collaboration
Maven Silicon
Maven Silicon

Articles

From Silos to Systems, from Data to Insight
Security certification and the crucial role of anti-tamper sensor solutions
Agile Analog
Chris Morrison
Agile Analog
Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight
Siemens - Tessent Embedded Analytics
Francisca Tan, Senior Product Manager
Siemens - Tessent Embedded Analytics
Three Ethernet Design Challenges in Industrial Automation
Key ASIC
Key ASIC
ST silicon photonics and BiCMOS technologies: the winning portfolio for AI optical interconnects
STMicroelectronics
STMicroelectronics
AI in VLSI Physical Design: Opportunities and Challenges
Japesh Kumar, Qualcomm
AI-Driven and Traditional Approaches to Accident Scenario Reconstruction
Vayavya Labs
Nitin Swamy
Vayavya Labs
From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security
PQSecure Technologies
PQSecure Technologies
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
Innosilicon Technology Ltd
Innosilicon Technology Ltd
Design Approaches and Architectures of RISC-V SoCs
Maven Silicon
Maven Silicon
Implementation of Metal ECO using Mask Programmable Cell for Hold Timing Violations
eInfochips, Inc.
Dhanyakumar Shah,Dharmik Lakhani
eInfochips, Inc.
Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
Menta
Menta
Asic Technology
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FPGA and eFPGA Corner
Select your target vendor and device
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