

How to cut power consumption for highspeed apps with A/D converter architectureIn short, CTΔ∑ technology means: 1. An inherently powerefficient architecture that eliminates powerhungry sampleandhold amplifiers (SHA) and the widebandwidth gain stages essential to the pipeline A/D converter concept. CTΔ∑ architecture supports highresolution analogtodigital conversion systems from 10 to 16bit and beyond with sampling rates up to 100 MHz. Today, most A/D converter design work aims to reduce power, particularly in highspeed conversion, and to minimize the number of comparators needed. It is broadly assumed that the pipeline converter provides the highest sample rates whilst yielding high dynamic range. It is used as a standard in data conversion applications at 10bit and higher resolutions and for sample rates from 5 MHz to 100 MHz or more. The architecture reduces the number of comparators needed by deploying multiple lowresolution flash conversion stages cascaded together to form the pipe. Although the resolution of each conversion stage is reduced, saving on comparators, the first stage must be designed with linearity at least as good as the maximum resolution of the A/D converter (12bit linearity for a 12bit A/D converter). Different pipeline implementations exist, but all work by reducing a multibit conversion into several lower resolution “flashes” that are processed synchronously. At each stage in the pipe, a reconstruction of the previous stage’s quantized output, generated by a D/A converter, is subtracted from the original input signal. The residual signal is then amplified prior to moving onto the following stage for finer quantization. In pipeline conversion a sampleandhold amplifier (SHA) is need to acquire the input signal and hold it to better than 0.5 LSB for the duration of the conversion. Once all substages have a valid conversion result, a digital correction block constructs the final multibit result. The pipeline A/D converter is capable of high dynamic performance. However, beyond 12bits resolution, as the sampled signal moves through the pipeline, transferring the charge associated with a given signal demands high gain bandwidth to ensure stage settling times fall within the limits set by the high frequency signals that are being sampled. To maintain linearity you need to calibrate and correct for the limits in component matching achievable with current process technologies and it is tough to migrate designs from one process to another. As operating voltages fall from one process generation to the next, the input signal headroom is compressed. Furthermore, designing switches with greatly reduced threshold voltages that work well in deep submicron processes gets harder. It’s worth remembering that pipeline A/D converters form only part of a data conversion system, you need in addition to find a low jitter clock source and design input stages that include antialias filters. In antialias filter (AAF) design, steep attenuation characteristics are hard to achieve, tempting you to consider oversampling the signal of interest. Oversampling stretches the Nyquist zone, lowering demands on filter rolloff but the tradeoffs are increased system power and higher processing speeds demanded of the backend DSP system. With continuous time deltasigma conversion, on the other hand, you don’t need an AAF. Historical deltasigma conversionThe Δ∑ converter uses a lowresolution quantizer  often only 1bit  clocked at rates considerably greater than Nyquist demands. The quantizer creates a large number of lowresolution samples that, averaged over time, yield an increased dynamic range. The analog design is potentially straightforward, given the linearity of a 1bit (2 level) quantizer. In the digital domain, filtering and decimation are needed to reconstruct output data and remove outofband noise. Figure 1 shows the simplest single order Δ∑ modulator block. It comprises a summing node, integrator and comparator. The comparator’s output feeds a 1bit DAC that closes the modulator’s feedback loop. The modulator compares the input signal against a voltage reference level fed back from the DAC. The comparator is clocked at the oversampling frequency. Assuming enough loop gain, the modulator is a pulse stream, the density of ‘1s’ or ‘0s’ of which is a direct digital representation of the input signal. The DAC switches between Vref to close the control loop.
Figure 1 Simplest single order Δ∑ modulator block Quantization errors within the modulator limit dynamic range. For the Δ∑ A/D converter, resolution increases are gained by balancing the oversampling ratio, Δ∑ modulator order, and quantizer resolution. Oversampling allows sample frequency/SNR tradeoff and improves dynamic range (DR). It gives an SNR improvement of 6 dB (or 1bit’s worth) for every quadrupling of the sample rate but DR is more effectively increased by increasing the resolution of the quantizer and/or by adding more integration stages to the modulator. Noise shaping is a property of Δ∑ A/D converters resulting from the application of feedback that extends dynamic range. This feature is best illustrated by the mathematical analysis of the feedback control loop of the Δ∑ modulator as modeled in the frequency domain, illustrated in Figure 2.
Figure 2 Noise shaping of Delta Sigma modulator This model reveals the key value of the Δ∑ modulator. A closed loop modulator works as a highpass filter to quantization noise and as a lowpass filter to the input signal. The effect of this is a further increase in dynamic range of 9 dB for each doubling of the sample rate. Additional integrators within the loop can increase the steepness of the noise characteristic to give you further dynamic range increases. Figure 3 shows simulation results for the noise power density for the Δ∑ modulator used in a CTΔ∑ A/D converter. This FFT plot (with 65k points) of the modulator illustrates the noise power density (per FFT bin) relative to the input signal frequency. The simulation was driven with an input signal frequency of approximately 4.8 MHz. The minimum noise power density achieved by this modulator is 166 dBc/Hz (in the pass band). Note the characteristic of the out of band noise i.e. those frequencies above 20 MHz. Here noise power levels rise at the rate of 21 dB/octave, a telltale sign of a third order modulator. Deployed within this A/D converter design is a 16 levels, or 4bit, quantizer that delivers 14bit dynamic range at modest oversampling rates. Having established a modulator system capable of achieving these low noise levels, the next stage is to apply filtering to eliminate outofband noise, and decimation to resample the data.
Figure 3 Noise over power density simulation results A digital filter must reject all signal components within the serial data stream that occur beyond the Nyquist bandwidth. Simplistically, two frequency selective filter structures can be implemented in the digital domain. They are the finite and infinite impulse response filter systems (FIR and IIR). FIRs are more widely used because they are simpler and have a linear phase response. IIR filter design is more complicated by virtue of the feedback included. The potentially infinite response of the IIR filter means there is always a possibility for the filter to become unstable. In addition, group delay can become significant and have adverse effects on performance in some systems. Many degrees of freedom exist for optimization of the signal transfer function in a CTΔ∑ A/D converter through combining different filter algorithms, however optimal solutions may require many cascaded stages of FIR and IIR sections. Digital filtering allows for the data reduction or downsampling necessary to provide output data at the originally intended sample rate. Note that oversampling provides large amounts of redundant data. The process of sample rate reduction is called decimation. In summary, these are the basic elements of a deltasigma A/D converter. Firstly, oversampling spreads quantization noise. Secondly, noise shaping reduces the inband noise at the expense of higher outofband noise. Thirdly, digital filtering attenuates outofband noise and signal components. Continuous time versus discrete time systems Pipeline and DTΔ∑ A/D converters have a common design thread. In discrete time, sampling an input signal requires that the signal be acquired at a precise moment in time. For an accurate representation of the input signal to be acquired on a hold capacitor, it is necessary that the input stages settle to a finite level, dictated by the accuracy limits of the system, in a time period driven by the system sample rate needs. This settling time eats into the sample time period of the system. At 40 MS/s a conversion system will have a sample period of just 25 ns, which sets the maximum time limits for circuit settling. At higher resolutions this drives a need for very high gain bandwidth circuits within the acquisition signal path. In fact, the converter system must be designed with circuits that work with bandwidths many times that of the input signal. Discrete time circuits therefore have to burn excess power to process a given bandwidth. The move to a continuous time strategy eliminates the settling time issue altogether, allowing either a lower power CTΔ∑ A/D converter implementation, versus discrete time, at a given sample rate or a higher sample rate for a given power budget. The continuous time implementation With CTΔ∑ the filter performance is dependent on conventional active filter design rules. If the sample rate is changed to match input signal bandwidth the CT filter must be tuned. Therefore, a potential limit on the CTΔ∑ implementation is how to ensure that a wide range of sample rates can be supported from a single product platform. This problem is solved using adaptive filter networks in combination with calibration techniques. For highresolution implementations the loop filter must have significant gain to obtain high linearity. This is provided using multipath and cascaded gain stages operating at 1.2 V and delivering 80 dB of gain for a 30 MHz bandwidth. This has been clearly demonstrated as possible in 0.13 ìm CMOS. The first product to implement CTΔ∑ conversion offers a low power alternative to the pipeline converter. It is said to be a complete data conversion system, designed to operate seamlessly over a wide range of sample rates without highperformance, expensive, external components. Highlights of this architecture include: Advantages of CTΔ∑ implementation Power consumption some 50% lower than the best existing pipeline designs Inherent antialias filtering simplifies the A/D converter input circuit
Figure 4 CT Δ∑ A/D converter eliminates complex input filtering High dynamic range and low oversampling rates Xignal uses a thirdorder CTΔ∑ modulator, designed around a 4bits quantizer stage helping it to achieve considerable dynamic range at an oversampling rate of 16. The differential input signal path has a bandwidth of 30 MHz. The internal sample clock operates at 640 MHz. The base technology today allows for increased sample rates to 80 MSPS (at 14bits) with an oversampling clock rate of approximately 1.3 GHz. Through selfadaptive tunable loop filter components the A/D converter is optimized for sample rates from 20 to 40 MSPS. A low jitter PLL provides an accurate sample clock Alternatively, an external clock can drive the A/D converter. High frequency jitter from an external distributed clock tree will be removed provided its jitter falls outside the 350 kHz PLL bandwidth of the jitter cleaner circuit. However, a further advantage of the onchip precision clock is that it can be routed to external circuits and used as a system reference clock for other timecritical parts of the system, potentially eliminating the extra cost of a low jitter source, saving both design effort and board area. A low jitter clock is a crucial function in all highspeed, highresolution data conversion systems. Phase accuracy of the sample clock has a major impact on measured performance. In fact, decibels of dynamic range are easily sacrificed by picoseconds of phase jitter. Figure 5 shows the mathematical derivation of maximal clock jitter for a given resolution and input signal frequency. For a 10 MHz bandwidth signal, at 12bit resolution, clock jitter must be less than 3 ps RMS. For 14bits, this demand drops to 1 ps RMS.
Figure 5 Maximal clock jitter Summary The quantization noise simulation result illustrated by Figure 3 hints at the unrealized dynamic range of a multibit Δ∑ modulator. There is some room for further dynamic range improvements with careful design, particular with respect to thermal noise, the dominant noise source in this design today. The ongoing development at Xignal shows that the A/D converter core can be successfully combined with input signal path components to provide a high level of integration. The digital processing (filtering and decimation) provided also shows that in future it is possible for system designers to tailor transfer functions for a given application. Finally, the elimination of external antialias networks and the inclusion of a high performance PLL significantly ease the design of a highresolution highspeed sampling system. Though complex, the technology deployed CTΔ∑ A/D converter has been implemented in such a way to be transparent to the user, making this one of the most complete and easiesttouse data acquisition systems available. Its implementation challenges some of the key assumptions made by designers developing high performance data conversion systems and offers a unique alternative. About the authorMark Holdaway is the director of product marketing for analog to digital converters at Xignal Technologies GmbH. You can contact him at mark.holdaway@xignal.de 
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